Multiple-port memory systems and methods
US8316192B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2009 |
| Grant date | Nov 20, 2012 |
| Priority date | — |
| Expiry date | Sep 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for improved multiple-port memory are provided. In one embodiment, a processing system comprises: at least one processing core; a peripheral bus; and a memory for storing digital data, the memory divided into a first and a second partition of memory segments. The memory includes a first port coupled to the peripheral bus providing read access and write access only to the first partition, wherein the first partition stores peripheral data associated with one or more peripheral components coupled to the peripheral bus; a second port coupled to the at least one processor providing read-only access to only the second partition, wherein the second partition stores executable code for the at least one processing core; and a third port coupled to the at least one processor providing read access and write access to the entire first partition and the second partition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.