Memory system that detects bit errors due to read disturbance and methods thereof
US8316278B2 · kind B2 · utility
14Cited by
18References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2008 |
| Grant date | Nov 20, 2012 |
| Priority date | — |
| Expiry date | Sep 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and memory systems are provided that detect bit errors due to read disturbances. A main page of a flash memory in a memory system is read. A bit error in data that is read from the main page is detected and corrected. In parallel with reading the main page, a bit error is detected in data that is read from a dummy page of the flash memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.