Method and mechanism for modeling interconnect structures for integrated circuits
US8316336B1 · kind B1 · utility
0Cited by
24References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2009 |
| Grant date | Nov 20, 2012 |
| Priority date | — |
| Expiry date | Jun 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are methods, systems, and structures for implementing interconnect modeling by using a test structure which include a variation of physical wire structures between local interconnects and distant interconnects. According to one approach, the impact of variations of the physical properties for neighborhood wires are considered for the electrical modeling of interconnects. This variation between the local and distant wire characteristics allows more accurate and robust interconnect modeling to be created.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.