Method for forming gate structures
US8318552B2 · kind B2 · utility
1Cited by
19References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 20, 2008 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Dec 25, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/441
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming gate structures is described. A web comprises a substrate, a plurality of conductive elements disposed on the substrate, and a conductive anodization bus. The web is moved through an anodization station to form a plurality of gate structures comprising a plurality of gate dielectrics adjacent to a plurality of gate electrodes. A process for forming electronic devices further providing a semiconductor, a source electrode, and a drain electrode is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.