Isolating wire bonding in integrated electrical components
US8318580B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2010 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Jan 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electrical component includes a semiconductor layer having a first conductivity type and a interconnect layer disposed adjacent to a frontside of the semiconductor layer. At least one bond pad is disposed in the interconnect layer and formed adjacent to the frontside of the semiconductor layer. An opening formed from the backside of the semiconductor layer and through the semiconductor layer exposes at least a portion of the bond pad. A first region having a second conductivity type extends from the backside of the semiconductor layer to the frontside of the semiconductor layer and surrounds the opening. The first region can abut a perimeter of the opening or alternatively, a second region having the first conductivity type can be disposed between the first region and a perimeter of the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.