Printed circuit board with reduced dielectric loss
US8319113B2 · kind B2 · utility
7Cited by
16References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2010 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Dec 12, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A printed circuit board (‘PCB’) with reduced dielectric loss, including conductive traces disposed upon layers of dielectric material, the layers of dielectric material including core layers and prepreg layers, one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.