Non-volatile semiconductor memory devices having charge trap layers between word lines and active regions thereof
US8319276B2 · kind B2 · utility
2Cited by
4References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2010 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Dec 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A non-volatile memory device includes: word line disposed on a substrate; an active region crossing over the word line; and a charge trap layer that is between the word line and the active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.