Wafer arrangement and a method for manufacturing the wafer arrangement
US8319302B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2007 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Mar 23, 2028 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2203/051
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The wafer arrangement (100) provided comprises a first wafer (101), which comprises an integrated circuit and a recess (105). The wafer arrangement further comprises a portion of a second wafer (103), which comprises a carrier portion and a protrusion (107), the protrusion comprising an active component or actively controlled component (109) such as a MEMS component, wherein the portion of the second wafer (103) is coupled to the first wafer (101) such that the protrusion (107) is received in the recess (105). The invention provides a mechanism for accurately aligning an active component (109) on the second wafer (103) with components on the first wafer (101), such as photonic, electronic or optical components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.