Depletion MOS transistor and enhancement MOS transistor
US8319316B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2010 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Feb 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
Abstract
A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.