Nonvolatile semiconductor memory device
US8320157B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2010 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Jun 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of first wirings, a plurality of second wirings intersecting the plurality of first wirings, and a plurality of memory cells provided at the intersections of the plurality of first and second wirings and each including a non-ohmic element and a variable resistance element connected in series. The control circuit selects one of the plurality of memory cells, generates an erasing pulse for erasing data from the selected memory cell, and supplies the erasing pulse to the selected memory cell. The control circuit executes data erase by applying a voltage of the erasing pulse to the non-ohmic element in the reverse bias direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.