Memory circuit and method of writing data to and reading data from memory circuit
US8320195B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2010 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Feb 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A disclosed memory circuit includes first and second latch circuits, each writing a write data at a timing of a clock signal and retaining the write data, the write data having been input in each of the first and second latch circuits, a data input circuit supplying the write data to each of the first and second latch circuits when a write enable signal indicates a state allowing the write data to be written, a write back circuit supplying the write data retained in the second latch circuit to the first latch circuit when the write enable signal indicates a state preventing the write data from being written, wherein a robustness against noise in the second latch circuit is more improved than that in the first latch circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.