Fully compensated adaptive interference cancellation system
US8320504B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2010 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Jun 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03273
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system for removing interference comprising a receive decimation filter that accepts a composite received baseband signal and generates filtered sampled data at a decimation rate, a transmit decimation filter that accepts a digitally converted replica of an interfering signal and generates filtered sampled data at a decimation rate, an integer sample delay control (ISDC) that provides multiple sample delay control for the replica and stores an estimated delay value, an adaptive filter that provides fractional sample delay control for the replica of the interfering signal and optimizes cancellation of the interfering signal, a digital phase-locked loop (DPLL) programmed with a known frequency offset of the interfering signal that tracks a phase and frequency of the replica of the interfering signal, an automatic gain control (AGC) that maintains near full scale operation of adaptive filtering and the DPLL, and a slicer, mixer, and delay unit forming an error estimator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.