Preamble acquisition without second order timing loops
US8320512B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2011 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Nov 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.