Clock and data recovery for differential quadrature phase shift keying
US8320770B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 22, 2010 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Mar 13, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/22
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method includes receiving a first input stream, generating a first clock, sampling the first input stream based on the first clock, detecting a first phase difference between the first input stream and the first clock to generate a clock-correction signal and a first select signal, and generating a first recovered stream based on the first select signal. The method may additionally include receiving a second input stream, generating a second clock, sampling the second input stream based on the second clock, detecting a second phase difference between the second input stream and the second clock to generate a clock-correction signal and a second select signal, and generating a second recovered stream based on the second select signal. The method may further include adjusting the clocks based on the first and second clock-correction signals and combining the first and second recovered data streams to generate an output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.