Systems and methods for managing memory using multi-state buffer representations
US8321606B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2011 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Oct 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0837
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are techniques to manage access to a memory using a buffer construct that includes state information associated with a region of the memory. The disclosed techniques facilitate access to the region of memory through a direct memory access operation while the state information of the buffer construct is in a first state. The state information can be transitioned to a second state in response to a first instruction. The disclosed techniques also facilitate access to the region of memory through a cache operation while the state information of the buffer construct is in the second state is disclosed. The state information can be transitioned to the first state in response to a second instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.