Power-saving control circuit and method
US8321609B2 · kind B2 · utility
1Cited by
12References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2006 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Feb 15, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power-saving control circuit and method suitable for circuits including a first-in-first-out (FIFO) register is provided. In the present invention, a logic circuit is disposed between two circuit modules with data transmitted in between. When there is data input into the FIFO register, the logic circuit activates a clock signal of the circuit module in the receiving end for reading the data. When all the data stored in the FIFO register is read, the clock signal is turned off so that the power consumed by the clock signal is reduced without affecting the data transmitting efficiency and the purpose of power-saving is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.