Dynamic scheduling interrupt controller for multiprocessors
US8321614B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 24, 2009 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Mar 28, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies are generally described herein for handling interrupts within a multiprocessor computing system. A priority level associated with a current task for each processor of the multiprocessor computing system can be maintained. Cache state information associated with each processor can also be maintained. Upon receiving an interrupt to the multiprocessor computing system, a cache locality score for each processor can be determined based on the maintained cache state information. A value can be computed that balances, for each processor, the priority level and the cache locality score. A processor for servicing the interrupt can be determined based on the computed value. The determined processor can be signaled to service the interrupt. Tracking state information related to processor cores can support rapid allocation of an arriving interrupt to a processor core without collecting processor core state information at interrupt time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.