Memory operation command latency management
US8321627B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2011 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Oct 6, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for managing latency of memory commands are disclosed. An example method includes receiving memory operation commands for execution by a data storage device, each memory operation command being associated, for execution, with one of a plurality of memory devices. The example method also includes maintaining, for each memory device, a respective cumulative latency estimate. The example method also includes, for each memory operation command, when received by the memory controller, comparing the respective cumulative latency estimate of the associated memory device with a latency threshold for the received memory operation command. In the event the cumulative latency estimate is at or below the latency threshold, the received memory operation command is provided to a respective command queue operatively coupled with the respective memory device. In the event the cumulative latency estimate is above the latency threshold, the received memory operation command is returned to a host device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.