System and method for designing architecture for specified permutation and datapath circuits for permutation
US8321823B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2008 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Sep 28, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/766
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer-implemented systems and methods that provide an efficient technique for performing a large class of permutations on data vectors of length 2n, n>1, implemented with streaming width 2k (where 1≦k≦n−1). The technique applies to any permutation Q on 2n datawords that can be specified as a linear transform, i.e., as an n×n bit matrix (a matrix containing only 1s and 0s) P on the bit level. The relationship between Q and P is as follows: If Q maps (dataword) i to (dataword) j, then the bit representation of j is the bit-matrix-vector product of P with the bit representation of i. Given such a permutation specified by the matrix P and given the streaming width (k), an architectural framework (or datapath) is calculated to implement the permutation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.