Virtual architecture and instruction set for parallel thread computing
US8321849B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2007 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Jul 30, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45533
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A virtual architecture and instruction set support explicit parallel-thread computing. The virtual architecture defines a virtual processor that supports concurrent execution of multiple virtual threads with multiple levels of data sharing and coordination (e.g., synchronization) between different virtual threads, as well as a virtual execution driver that controls the virtual processor. A virtual instruction set architecture for the virtual processor is used to define behavior of a virtual thread and includes instructions related to parallel thread behavior, e.g., data sharing and synchronization. Using the virtual platform, programmers can develop application programs in which virtual threads execute concurrently to process data; virtual translators and drivers adapt the application code to particular hardware on which it is to execute, transparently to the programmer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.