Electronic system and method for manufacturing a three-dimensional electronic system
US8324022B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2008 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Apr 27, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a three-dimensional, electronic system includes: providing a first integrated circuit structure in a first substrate, wherein the first integrated circuit structure has a first contact pad at a first main side of the first substrate; providing a second substrate with a second main side; forming a vertical contact area in the second substrate; after step (c) forming a semiconductor layer on the second main side of the second substrate; forming a semiconductor device of a second integrated circuit structure in the second substrate with the semiconductor layer; removing the substrate material from a side of the second substrate opposite the second main side, so that the vertical contact area at the opposite side is electrically exposed; arranging the first and second substrates on top of each other aligning the vertical contact area with the contact pad, so that an electrical connection between the first and second integrated circuit structures is produced via the vertical contact area and the contact pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.