Method and structure of an integrated CMOS and MEMS device using air dielectric
US8324047B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 13, 2010 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Jun 10, 2031 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81B2207/015
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
In a specific embodiment, the present invention provides an integrated circuit device. The device includes a base substrate having a surface region and an interlayer dielectric material overlying the surface region. The device also has a thickness of single crystal silicon material overlying the interlayer dielectric material. In one or more embodiments, the thickness of single crystal silicon material has a front region and a backside region. The front region faces the interlayer dielectric material. In a preferred embodiment, the device has a plurality of transistor devices spatially arranged in the thickness of silicon crystal silicon material. Each of the transistor devices has a gate structure within a region of the interlayer dielectric material. The device also has an enclosure housing configured to form a cavity between the backside region of the thickness of silicon material and an upper inside region of the enclosure housing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.