Non-volatile semiconductor device and method of fabricating embedded non-volatile semiconductor memory device with sidewall gate
US8324092B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2010 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Feb 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0425
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.