Reduction of electrostatic coupling for a thyristor-based memory cell
US8324656B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2011 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Jul 1, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D18/251
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of integrated circuits for mitigating against electrostatic coupling are described. In an embodiment, first gate dielectrics are respectively located over first active regions. First isolation regions are respectively located between the first active regions. Second gate dielectrics are respectively located over second active regions. Second isolation regions are respectively located between the second active regions. In an embodiment, the first active regions are approximately 20 to 80 percent shorter in height/thickness than the second active regions. In another embodiment, the first isolation regions extend above an uppermost surface of the first gate dielectrics while providing gaps between the first isolation regions and sidewalls of the first active regions for receipt of material used in formation of conductive lines. In yet another embodiment, active area stripes are narrower in width at p-base regions and n-base regions than at cathode regions and anode regions respectively thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.