Dynamic random access memory cell and array having vertical channel transistor
US8324682B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2011 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Feb 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/056
Abstract
A dynamic random access memory cell having vertical channel transistor includes a semiconductor pillar, a drain layer, an assisted gate, a control gate, a source layer, and a capacitor. The vertical channel transistor has an active region formed by the semiconductor pillar. The drain layer is formed at the bottom of the semiconductor pillar. The assisted gate is formed beside the drain layer, and separated from the drain layer by a first gate dielectric layer. The control gate is formed beside the semiconductor pillar, and separated from the active region by a second gate dielectric layer. The source layer is formed at the top of the semiconductor pillar. The capacitor is formed to electrical connect to the source layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.