Self aligned field effect transistor structure
US8324689B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2009 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Dec 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0241
Abstract
Provided is a self aligned field effect transistor structure. The self aligned field effect transistor structure includes: an active region pattern on a substrate; a first gate electrode and a second gate electrode facing each other with the active region pattern therebetween; and a source electrode and a drain electrode connected to the active region pattern and disposed to be symmetric with respect to a line connecting the first and second gate electrodes, wherein the first and second gate electrodes and the source and drain electrodes are disposed on the same plane of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.