Automatic on-chip detection of power supply configuration-modes for integrated chips
US8324756B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2008 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Feb 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31721
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A power management (PM) system architecture for a controlled SoC detects availability of power supply for signal-driving at a given node inside a chip, and uses a timer, a discharge mechanism with trigger for starting/stopping a discharge process, and a comparator for monitoring a measured voltage of an intended node during the discharge process. Enabling the discharge mechanism for a known time period helps detection. Power supply can be internally generated in the chip or from a source on board. The architecture detects if the node is driven or floating, an undriven floating node causing a dip in the measured voltage. The measured voltage does not have a dip when the node is driven. The architecture is also configured so that when there is a required on-board external power supply, an internal power supply is disabled to avoid a race-condition. The architecture obviates a dedicated IO pin for mode-indication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.