Patent · US Active

High speed multiple memory interface I/O cell

US8324927B2 · kind B2 · utility

3Cited by

4References

20Claims

0Family size

Assignee

LSI · US

Inventors

Dharmesh Bhakta · Austin, US
Hong-Him Lim · Cupertino, US
Cheng-Gang Kong · Saratoga, US
Todd A. Randazzo · Colorado Springs, US

Key dates

Filing date	Dec 16, 2010
Grant date	Dec 4, 2012
Priority date	—
Expiry date	Dec 16, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/2254
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.