Time-to-digital converter
US8325076B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Sep 11, 2007 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Sep 1, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Time-to-Digital Converter (TDC) is constructed using simple digital delay circuits. The design uses a clock compensation scheme to modify and adjust the TDC's operation under integrated circuit fabrication process variations. The TDC design is based on a novel digital processing algorithm that produces one conversion every clock cycle. Therefore, this TDC is the “first” single cycle latency TDC targeted at high speed circuit applications such as (but not limited to) time-based Analog to Digital Converters (ADCs) for direct analog to digital conversion of radio frequency signals in wireless communication systems and high speed signal measurement applications. Due to its hierarchical design approach, the TDC design uses an optimized number of delay circuits and therefore requires very little power consumption and silicon area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.