Power amplifier, and method of controlling power amplifier
US8326244B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2008 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Jan 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/7236
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power amplifier of the present invention comprises MOS transistor (1) having a gate length of 180 nm or less, and output matching circuit (5) connected to a drain terminal of MOS transistor (1). Also, MOS transistor (1) is applied with voltage Vd_n normalized by a voltage value allowable in a DC state as a drain-source voltage, where Vd_n is in a range of 0.5 to 0.9. ZL (=RH+j·XL) represents a value equal to a load impedance when viewing the output matching circuit (5) from the drain terminal normalized by gate width W (mm) of MOS transistor (1), and a real part (RL) of the ZL is RL>0.64×Vd_n+0.19 (Ω·mm), and RL<0.64×Vd_n+1.73 (Ω·mm).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.