Patent · US Active

High resolution, low power design for CPRI/OBSAI latency measurement

US8326364B2 · kind B2 · utility

1Cited by

7References

19Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Gary F. Chard · Garland, US
T-Pinn R. Koh · Allen, US
Yilun Wang · Auckland, NZ

Key dates

Filing date	May 13, 2010
Grant date	Dec 4, 2012
Priority date	—
Expiry date	Jul 16, 2031

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D30/70
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.