Synchronized envelope and transient simulation of circuits
US8326591B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2007 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Apr 13, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a method of simulating a circuit is disclosed including partitioning a circuit into a plurality of blocks, each of the plurality of blocks being radio-frequency blocks or non-radio frequency blocks; performing a first simulation of a first simulation type with the radio-frequency blocks to generate output waveforms of the radio-frequency blocks; performing a second simulation of a second simulation type with the non-radio-frequency blocks to generate output waveforms of the non-radio-frequency blocks where the second simulation type differs from the first simulation type; and synchronizing the first simulation and the second simulation together at one or more time steps to generate output waveforms for the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.