Transversal filter circuit with a plurality of delay units, multiplexers, and full adders suited for a smaller decision feedback equalizer
US8326905B2 · kind B2 · utility
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4References
20Claims
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Key dates
| Filing date | May 22, 2009 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Sep 1, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transversal filter circuit comprises a plurality of delay units, a plurality of multiplexers and a plurality of full adders. The plurality of delay units is coupled in series to delay a two-bit input signal. The plurality of multiplexers is coupled to the plurality of delay units in a one-to-one manner, and outputs zero, a data signal, or the inverse of the data signal according to the output signals of the plurality of delay units. The plurality of full adders accumulates the outputs of the plurality of multiplexers and the MSB of the outputs of the plurality of the delay units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.