Microprocessor systems
US8327034B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2004 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | May 22, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A slave device (20) communicates with a host system (21) via a host communications bus (22). The host system (21) includes one (or more) processing units that can act as bus masters and send access requests for slave resources on the slave device (20) via the communications bus (22). The slave device platform (20) includes a memory management unit (23), a programmable central processing unit (24) and one or more slave resources (25). The memory management unit (23) acts as an address translating device, and accepts requests with virtual addresses from the master device or devices on the host system (21), translates the virtual addresses used in the access requests to the “internal” physical addresses of the slave's resources and forwards the accesses of the appropriate physical resources (25). When an address miss occurs in the memory management unit (23), it passes the handling of the access request over to the controlling CPU (24) which executes software to then resolve the address miss and handle the access request. The memory management unit (23) also includes a write buffer (29) into which it can write the write value received from a master on the host system (21) on an access…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.