Cache memory control device and pipeline control method
US8327079B2 · kind B2 · utility
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4References
11Claims
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Key dates
| Filing date | Dec 11, 2009 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Sep 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0857
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory control device includes: a determination unit for determining whether or not a command provided from, for example, each core is to access cache memory during the execution of the command; and a path switch unit for putting a command determined as accessing the cache memory in pipeline processing, and outputting a command determined as not accessing the cache memory directly to an external unit without putting the command in the pipeline processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.