Transparent hypervisor pinning of critical memory areas in a shared memory partition data processing system
US8327083B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2012 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Jan 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0745
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Transparent hypervisor pinning of critical memory areas is provided for a shared memory partition data processing system. The transparent hypervisor pinning includes receiving at a hypervisor a hypervisor call initiated by a logical partition to register a logical memory area of the logical partition with the hypervisor. Responsive to this hypervisor call, the hypervisor transparently determines whether the logical memory is a critical memory area for access by the hypervisor. If the logical memory area is a critical memory area, then the hypervisor automatically pins the logical memory area to physical memory of the shared memory partition data processing system, thereby ensuring that the memory area will not be paged-out from physical memory to external storage, and thus ensuring availability of the logic memory area to the hypervisor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.