Apparatus and method for executing fast bit scan forward/reverse (BSR/BSF) instructions
US8327119B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 21, 2009 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Oct 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3017
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus executes a bit scan instruction that specifies an N-byte input operand. A first encoder forward bit scan encodes each input byte to generate N first bit vectors. A zero detector zero-detects each input byte to generate a second bit vector. A second encoder forward bit scan encodes the second bit vector to generate a third bit vector. An N:1 multiplexor, controlled by the third bit vector, selects one of the N first bit vectors to output a fourth bit vector. The apparatus concatenates the third and fourth bit vectors into a fifth bit vector that indicates the bit index of the least significant set bit of the input operand. A third encoder forward bit scan encodes a bit-reversed version of each input by to generate N sixth bit vectors. A fourth encoder forward bit scan encodes a bit-reversed version of the second bit vector to generate a seventh bit vector. A second N:1 multiplexor, controlled by the seventh bit vector, selects one of the N sixth bit vectors to output an eighth bit vector. Selection logic selects a concatenation of the third and fourth bit vectors into the fifth bit vector if an input indicates forward bit scan, and the selection logic selects an inverte…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.