Mechanism for adjacent-symbol error correction and detection
US8327222B2 · kind B2 · utility
0Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Jan 15, 2009 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Oct 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment a computer system is disclosed. The computer system includes memory. The memory includes two or more rows, where each row has a plurality of memory devices. The computer system also includes a chipset. The chipset includes a detection/correction circuit to detect single and double symbol errors and correct single symbol errors for each memory row, and markers to maintain a log of errors within each memory row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.