Method and system for eliminating implementation timing in synchronization circuits

US8327307B2 · kind B2 · utility

Assignee

• LSI · US

Inventors

• Christian Krönke · Langenhagen, DE
• Ansgar Bambynek · Munich, DE
• Jurgen Dirks · Bochum, DE

Key dates

• Filing date: Nov 23, 2010
• Grant date: Dec 4, 2012
• Expiry date: Feb 10, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L7/02
• WIPO field: Digital communication
• WIPO sector: Electrical engineering

Abstract

A method and system for eliminating implementation timing with respect to a synchronization circuit. A standard library cell having a pair of clock input pins can be connected with at least two asynchronous clock domains of the synchronization circuit in order to measure a timing signal between the flip-flop latches crossing the asynchronous clock domain. A timing delay with respect to each bit pair of the asynchronous clock domain can be determined utilizing a static analysis approach during a layout phase in order to effectively synchronize the asynchronous clock domain. Each bit pair of the asynchronous clock domain can be checked via a static timing analysis tool in order to thereby improve functional accuracy of the synchronization circuit in a wide range of digital logic designs.