Mask design elements to aid circuit editing and mask redesign
US8330159B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2007 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Oct 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.