Intrusion protection using stress changes
US8330191B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2009 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Nov 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a integrated circuit comprising an electronic circuit integrated on a substrate (5), and further comprising protections means for protection of the electronic circuit (25). The protection means comprise: i) a first strained encapsulation layer (10) being provided on a first side of the substrate (5), wherein the first strained encapsulation layer (10) has a strain (S1) in a direction parallel to the substrate (5), and ii) disabling means (20) arranged for at least partially disabling the electronic circuit (25) under control of a strain change in the substrate (5). The invention further relates to a method of manufacturing such integrated circuit, and to a system comprising such integrated circuit. Such system is selected from a group comprising: a bank-card, a smart-card, a contact-less card and an RFID. All embodiments of the integrated circuit in accordance with the invention provide essentially an alternative tamper protection to the data stored or present in the electronic circuit therein. A first main group of embodiments concerns an integrated circuit wherein tamper protection is obtained by detecting a strain change during tampering and subsequently…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.