Dynamic biasing systems and methods
US8330504B2 · kind B2 · utility
21Cited by
2References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 4, 2011 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | May 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/145
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Dynamic biasing methods and circuits are described. The described methods generate bias voltages that are continuously varied so as to control stress voltages across transistors used within a cascode stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.