Low consumption flip-flop circuit with data retention and method thereof
US8330518B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 18, 2011 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Jan 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.