Systems and methods for saturation correction in a power control loop
US8330546B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2012 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | May 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power amplification circuit includes a power amplifier, an RF detector, an error amplifier, a saturation detector, and an offset circuit. The power amplifier provides an amplified signal based on an input signal and a gain control signal. The RF detector provides a detection signal indicative of a logarithm of the power of the amplified signal. The error amplifier provides the gain control signal based on an amplification control signal and the detection signal. The saturation detector provides a saturation signal in response to the gain control signal differing from a reference signal by less than a first predetermined voltage. The offset circuit decreases a voltage level of the amplification control signal by up to a second predetermined voltage in response to the saturation signal and the amplification control signal differing from the detection signal by less than the second predetermined voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.