Semiconductor device and information processing system including the same
US8331122B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2010 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Jun 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16225
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes plural core chips and an interface chip that controls the plural core chips. Each of the plural core chips includes a layer address generating circuit that generates a second chip address by incrementing a value of a first chip address and a layer address comparing circuit that compares a third chip address supplied from the interface chip and the second chip address, and activates a chip selection signal when the third chip address and the second chip address are matched with each other. When a non-used chip signal is in an inactivated state, the layer address generating circuit supplies the second chip address to another core chip, and when the non-used chip signal is in an activated state, the layer address generating circuit supplies the first chip address to another core chip without a change.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.