Apparatuses for register file with novel bit cell implementation
US8331133B2 · kind B2 · utility
1Cited by
3References
29Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 26, 2009 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Feb 7, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Approaches to organizing/constructing a register file base cell in a way that reduces the number of signals which need to be routed to and through the bit base cell are disclosed. Base cells so constructed allow industry standard static timing approaches and tools to verify the timing of a register file comprised of such base cells as a whole and allow industry standard place-and-route (APR) tools to be used to implement the connections between the base cells and the other register file logic not directly included in the base cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.