SRAM compatible embedded DRAM system with hidden refresh and dual port capabilities
US8331184B2 · kind B2 · utility
6Cited by
3References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 23, 2010 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Feb 8, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM compatible embedded DRAM system with hidden refresh and dual port capabilities includes a memory cell array comprised of a plurality of single-port memory cells with dual-port capability, a first and a second port access units connected to the memory cell array in order to access the memory cells, and an access arbiter connected to the first and the second port access units in order to arbitrate a first port access request, a second port access request and a hidden refresh request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.