Clock data restoration device
US8331513B2 · kind B2 · utility
2Cited by
3References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 28, 2008 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Apr 12, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03012
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock data restoration device 1, which restores a clock signal and data on the basis of an inputted digital signal, comprises an equalizer 10, a sampler 20, a clock generator 30, an equalizer controller 40, and a phase monitor 50. A clock signal CK or CKX as a clock signal restored on the basis of the input digital signal is generated through loop processing by the sampler 20 and the clock generator 30. The level adjustment amount of a high frequency component of the digital signal by the equalizer 10 is controlled through loop processing by the equalizer 10, the sampler 20 and the equalizer controller 40.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.