Pattern detection circuitry
US8331581B2 · kind B2 · utility
46Cited by
7References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 16, 2011 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Nov 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pattern detection circuit detects a pattern in a received bit stream, for example a repetitive 8-bit silence pattern in a stream of digital audio data. Summing circuitry forms during first alternate time periods a sum of a first sequence comprising a predetermined number of alternate bits in the bit stream; and forms during second alternate time periods an inverse of a sum of a second sequence comprising the predetermined number of alternate bits in the bit stream. It is then determined whether successive sums formed by the summing circuitry are equal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.