Patent · US Active

Power-saving receiver circuits, systems and processes

US8331898B2 · kind B2 · utility

15Cited by

21References

19Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Deric Wayne Waters · Dallas, US
Karthik Ramasubramanian · Savanuru, IN
Arun Raghupathy · San Diego, US

Key dates

Filing date	Oct 2, 2008
Grant date	Dec 11, 2012
Priority date	—
Expiry date	Jun 18, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG01S19/34
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

An electronic circuit includes a receiver circuit (BSP) operable to perform coherent summations having a coherent summations time interval, and a power control circuit (2130) coupled to said receiver circuit (BSP) and operable to impress a power controlling duty cycle (TON, TOFF) on the receiver circuit (BSP) inside the coherent summations time interval. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.